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Guerrieri Andrea

Guerrieri Andrea

Professeur-e HES Associé-e

Main skills

Electonic Design Automation

Software-defined Hardware

Reconfigurable Architectures

Heterogeneous Computing

Embedded Systems

High-Level Synthesis

ASIC and FPGA design

  • Contact

  • Teaching

  • Research

  • Publications

  • Conferences

Main contract

Professeur-e HES Associé-e

Desktop: ENP.23.N312

HES-SO Valais-Wallis - Haute Ecole d'Ingénierie
Rue de l'Industrie 23, 1950 Sion, CH
HEI - VS
Faculty
Technique et IT
Main Degree Programme
Systèmes industriels

His research interests include reconfigurable computing, electronics design automation (EDA), and security.

He is the author of the fast compiler for FPGA DynaRapid, and the co-author of the High-Level Synthesis compiler Dynamatic, among other EDA tools for FPGAs ans reconfigurable platforms. The technology he developed and worked on during his career has been adopted by major semiconductor companies such as MIPS, Intel, and AMD-Xilinx.

He authored several dozens of papers presented at prestigious international venues such as the International Symposium of Field-Programmable Gate Arrays(ISFPGA), the Design Automation Conference (DAC), Space Computing Conference(SCC), and Quality Electronics Design (ISQED). He is also the author of a book on System-on-Chip Design with Arm, and editor of a book on Applications enabled by FPGA-based technology.

Andrea’s work has earned him several prestigious awards, including Best Paper Awards at FPL 2024, HPEC 2024, and ISFPGA 2020, held in Seaside, California. He has also received multiple Best Paper nominations at FCCM 2022 in New York, FPL 2022 in Edinburgh, and the European HiPEAC 2022 award. In 2021, he was recognized as a Senior Member of IEEE. Andrea actively serves as a Technical Program Committee (TPC) member, artifact evaluator, and session chair for key conferences such as DAC, DATE, ISFPGA, ICCD, FCCM, FPL, and ISQED. He was honored with the Outstanding TPC Member Award at DAC 2024 in San Francisco, California, USA.

He participates in and leads multiple international projects, and he is currently collaborating with partners across Switzerland and Silicon Valley (USA) to shape the next generation of EDA tools and reconfigurable computing platforms for both terrestrial and space applications. His key collaborators include industry giants like AMD-Xilinx, NVIDIA, Arm, NASA, and CERN, but also academic institutions such as ETH Zurich, University of Geneva, and California State University. He is chair of the Onboard Computing topic for the Swiss consortium CHEESE affiliated with NASA SSERVI (Solar System Exploration Research Virtual Institute), located at AMES Research Center, Mountain View, California, USA.

BSc HES-SO en Systèmes industriels - HES-SO Valais-Wallis - Haute Ecole d'Ingénierie
  • System-on-Chip
BSC HES-SO en Informatique et systèmes de communication - HES-SO Valais-Wallis - Haute Ecole d'Ingénierie
  • Digital Design
MSc HES-SO en Engineering - HES-SO Master
  • Embedded Hardware and Firmware

Completed

DyReCte - Dynamically Reconfigurable Cryptoengine

Role: Collaborator

Financement: Innosuisse

Description du projet :

Ce projet a deux objectifs : 1) Développer un cœur de calcul sur une architecture matérielle pour implémenter des algorithmes de cryptographie post-quantique et 2) Concevoir et implémenter une architecture FPGA dynamiquement reconfigurable pour des nano-satellites. Cette architecture fournira des capacités de tolérance aux pannes et permettra de sécuriser les communications entre le satellite et la terre.

Research team within HES-SO: Upegui Posada Andres , Berthet Quentin , Gantel Laurent , Guerrieri Andrea , Da Silva Marques Gabriel

Partenaires académiques: Duc Alexandre, HEIG-VD

Partenaires professionnels: Felk Yacine, Cysec S.A.

Durée du projet: 17.06.2019 - 17.06.2021

Montant global du projet: 417'770 CHF

Statut: Completed

2025

Srijeet Guha and Andrea Guerrieri, Precision Unwound: Fine-Tuning Loop Unrolling for Energy-efficient FPGA-based PQC using HLS
Scientific paper

Guerrieri Andrea

2025 26th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2025, 2025

2024

Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipović, and Paolo Ienne. DynaRapid: Fast- Tracking from C to Routed Circuits. [Best Paper Award]
Scientific paper

Guerrieri Andrea

In Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, Sept.2024, 2024

Summary:

Best Paper Award.

John Biselx, Andrea Guerrieri. Performance Analysis of Falcon Post-Quantum Cryptography in Embedded Hardware-Software Integration.
Scientific paper
[ Outstanding Short Paper Award ]

Guerrieri Andrea

IEEE Conference on High-Performance Extreme Computing HPEC. Sept. 2024., 2024

Srijeet Guha, Andrea Guerrieri. “Iterative Frequency Tuning Targeting Energy Efficiency Ratio for FPGA-Based Post-Quantum Cryptographic Cores".
Scientific paper

Guerrieri Andrea

31st IEEE International Conference on Electronics Circuits and Systems, Nov.2024, France, 2024

Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, and Lana Josipović. Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits.
Scientific paper

Guerrieri Andrea

In Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, Sept.2024., 2024

Andrea Guerrieri, David Rodriguez, and Edoardo Charbon, “A Dynamically Reconfigurable Single-Board Computer for High Dynamic Range Space Cameras"
Scientific paper

Guerrieri Andrea

in 2024 IEEE SMC-IT Conference on Space Mission Challenges for Information Technology, 2024, 15-19 July, Mountain View, California., 2024

Saverio Nasturzio, Michael Linder, Aziz Belkhiria and Andrea Guerrieri “COSMOS - Computational Optimization and Scheduling for Multi-tenant Orbital Services.”
Scientific paper

Guerrieri Andrea

in 2024 IEEE SCC Conference on Space Computing Challenges. 15-19 July, Mountain View, California., 2024

Capucine Berger-Sigrist and Andrea Guerrieri, "Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography,"
Scientific paper

Guerrieri Andrea

2024 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2024, 2024

Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Survival of the fastest: Enabling more out‐of‐order execution in dataflow circuits.
Scientific paper

Guerrieri Andrea

In Proceedings of the 32nd ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 44–54, Monterey, Calif., March 2024., 2024

Andrea Guerrieri, Srijeet Guha, Lana Josipović, and Paolo Ienne. DynaRapid: From C to FPGA in a few seconds.
Scientific paper

Guerrieri Andrea

In Proceedings of the 32nd ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 40, Monterey, Calif., March 2024. Abstract only., 2024

2023

Applications enabled by FPGA-based technology
Book ArODES

Andres Upegui, Andrea Guerrieri, Laurent Gantel

2023,  Basel : MDPI,  196 p.

Link to the publication

Summary:

This book is a reprint of the Special Issue Applications Enabled by FPGA-Based Technology that was published in Electronics.

Applications enabled by FPGA-based technology
Scientific paper ArODES

Andrea Guerrieri, Andres Upegui, Laurent Gantel

Electronics,  12, 15, 3302

Link to the publication

Applications Enabled by FPGA-Based Technology
Book

Upegui Posada Andres, Guerrieri Andrea, Gantel Laurent

2023,  Basel, Switzerland : MDPI,  198  p.

Link to the publication

H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware Accelerators
Scientific paper

Guerrieri Andrea, Da Silva Marques Gabriel, Francesco Regazzoni, Upegui Posada Andres

2023 24th International Symposium on Quality Electronic Design (ISQED), 2023

Link to the publication

Applications enabled by FPGA-based technology
Scientific paper

Guerrieri Andrea, Upegui Posada Andres, Gantel Laurent

Electronics,, 2023

Link to the publication

Lana Josipović, Axel Marmet, Andrea Guerrieri, and Paolo Ienne. Resource sharing in dataflow circuits.
Scientific paper

Guerrieri Andrea

ACM Transactions on Reconfigurable Technology and Systems (TRETS), 16(4):54:1–54:27, December 2023, 2023

Carmine Rizzi, Andrea Guerrieri, and Lana Josipović. An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits.
Scientific paper

Guerrieri Andrea

In Proceedings of the 60th Design Automation Conference, San Francisco, July‘23., 2023

2022

Design exploration and code optimizations for FPGA-based post-quantum cryptography using high-level synthesis
Scientific paper ArODES

Andrea Guerrieri, Gabriel da Silva Marques, Francesco Regazzoni, Andres Upegui

IEEEAccess,  2016, vol. 4

Link to the publication

Summary:

Design Exploration and Code Optimizations for FPGA-Based Post-Quantum Cryptography using High-Level Synthesis. In this paper we try to detect and address bottleneck and limitation of HLS while synthesizing general-purpose code for emerging applications such as post-quantum cryptography.

Resource Sharing in Dataflow Circuits
Scientific paper

Guerrieri Andrea

In Proceedings of Field Custom Computing Machines (FCCM), New York City, New York, USA, 2022

Design Exploration and Code Optimizations for FPGA-Based Post-Quantum Cryptography using High-Level Synthesis
Scientific paper

Guerrieri Andrea

IEEE Techrxiv, 2022

Link to the publication

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis
Scientific paper

Guerrieri Andrea, Da Silva Marques Gabriel, Francesco Regazzoni, Upegui Posada Andres

2022 25th Euromicro Conference on Digital System Design (DSD), 2022

Link to the publication

Design exploration and code optimizations for FPGA-based post-quantum cryptography using high-level synthesis
Scientific paper

Guerrieri Andrea, Da Silva Marques Gabriel, Francesco Regazzoni, Upegui Posada Andres

IEEEAccess, 2022 , vol.  4

Link to the publication

2021

Fundamentals of system-on-chip design on arm cortex-M microcontrollers
Book ArODES

René Beuchat, Florian Depraz, Andrea Guerrieri, Sahand Kashani

2021,  Cambridge : Arm Education Media,  xlvi, 608 pages

Link to the publication

Summary:

This textbook aims to provide learners with an understanding of embedded systems built around Arm Cortex-M processor cores, a popular CPU architecture often used in modern low-power SoCs that target IoT applications. Readers will be introduced to the basic principles of an embedded system from a high-level hardware and software perspective and will then be taken through the fundamentals of microcontroller architectures and SoC-based designs. Along the way, key topics such as chip design, the features and benefits of Arm’s Cortex-M processor architectures (including TrustZone, CMSIS and AMBA), interconnects, peripherals and memory management are discussed. The material covered in this book can be considered as key background for any student intending to major in computer engineering and is suitable for use in an undergraduate course on digital design.

From C/C++ Code to High-Performance Dataflow Circuits
Scientific paper

Guerrieri Andrea

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021

Link to the publication

Resource Sharing in Dataflow Circuits
Scientific paper

Guerrieri Andrea, Lana Josipovic, Axel Marmet, Paolo Ienne

In Proceedings of the 29th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Seaside, Calif., 2021

Link to the publication

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits.
Scientific paper

Lana Josipovic, Guerrieri Andrea, Paolo Ienne

IEEE Circuits and Systems Magazine, Special Issue FPGA Evolution, 2021 , vol.  21, no  2

Link to the publication

Fundamentals of SoC Design on Arm CortexM Microcontrollers
Book

Guerrieri Andrea, Rene' Beuchat, Sahand Kashani, Florian Depraz

2021,  UK : Arm Education media,  660  p.

Link to the publication

Summary:

This textbook aims to provide learners with an understanding of embedded systems built around Arm Cortex-M processor cores, a popular CPU architecture often used in modern low-power SoCs that target IoT applications. Readers will be introduced to the basic principles of an embedded system from a high-level hardware and software perspective and will then be taken through the fundamentals of microcontroller architectures and SoC-based designs. Along the way, key topics such as chip design, the features and benefits of Arm's Cortex-M processor architectures (including TrustZone, CMSIS and AMBA), interconnects, peripherals and memory management are discussed. The material covered in this book can be considered as key background for any student intending to major in computer engineering and is suitable for use in an undergraduate course on digital design.

2020

CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors
Scientific paper

Seyedeh Sharareh Mirzargar, Guerrieri Andrea, Mirjana Stojilovic

In Proceedings of the 28th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Seaside, Calif., 2020

Link to the publication

Buffer placement and sizing for high-performance dataflow circuits.
Scientific paper

Guerrieri Andrea, Lana Josipovic, Shabnam Sheikka, Paolo Ienne

In Proceedings of the 28th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 186–96, Seaside, Calif. BEST PAPER AWARD., 2020

Link to the publication

Dynamatic: From C/C++ to dynamically scheduled circuits.
Scientific paper

Lana Josipovic, Guerrieri Andrea, Paolo Ienne

In Proceedings of the 28th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 1–10, Seaside, Calif., 2020

Link to the publication

Noninstrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs.
Scientific paper

Seyedeh Sharareh Mirzargar, Gaetan Renault, Guerrieri Andrea, Miriana Stojilovic

In Proceedings of the IEEE International Conference on Field Programmable Technology, Maui, Hawaii, USA. December 2020, 2020

Link to the publication

2019

Performance Optimization of Dataflow Circuits
Scientific paper

Guerrieri Andrea

Design Automation Conference, Las Vegas, Nevada, 2019

Link to the publication

Performance Optimization of Dataflow Circuits
Scientific paper

Guerrieri Andrea

International Workshop on Logic & Synthesis (IWLS), Lausanne, Switzerland, 2019

Link to the publication

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips,
Scientific paper

Guerrieri Andrea, Sahand Kashani, Mikhail Asiatici, Paolo Ienne

IEEE Access, 2019

Link to the publication

Speculative dataflow circuits.
Scientific paper

Guerrieri Andrea, Lana Josipovic, Paolo Ienne

In Proceedings of the 27th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., 2019

Link to the publication

Shrink it or shed it! Minimize the use of LSQs in dataflow designs.
Scientific paper

Lana Josipovic, Atri Bhattacharyya, Guerrieri Andrea

In Proceedings of the IEEE International Conference on Field Programmable Technology, pages 197–205, Tianjin, China,, 2019

Link to the publication

2018

Software Initiated FPGA Threading.
Scientific paper

Guerrieri Andrea

Space Technologies Studies, Lausanne, Switzerland, 2018

Link to the publication

LEOSoC: An Open Source Embedded Linux Library for Managing Hardware Accelerators on Heterogeneous System on Chips.
Scientific paper

Guerrieri Andrea

FPGA Conference ’18, Monterey, California., 2018

An Extremely Fast Real-Time Computer for the Next Generation of Adaptive Optics Systems
Scientific paper

Guerrieri Andrea

RTC4AO5 Real Time Control for Adaptive Optics 5th edition, Paris,, 2018

Link to the publication

FPGA Based Multithreading for On-Board Processing.
Scientific paper

Guerrieri Andrea, Pasquale Lombardi, Bilel Beladj

SEFUW-18, Space FPGA User Workshop, ESA ESTEC, The Netherlands,, 2018

Link to the publication

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing
Scientific paper

Guerrieri Andrea, Sahand Kashani, Pasquale Lombardi, Bilel Beladj, Paolo Ienne

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, 2018

Link to the publication

2017

Designing a RFNoC Block implementing a SISO Processor using High-Level Synthesis.
Scientific paper

Guerrieri Andrea

GnuRadio Conference ’17, San Diego, California., 2017

Link to the publication

2024

Fast switching activity estimation for HLS-produced dataflow circuits
Conference ArODES

Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, Lana Jospipovic

Proceedings of the 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), 2-6 September 2024, Torino, Italy

Link to the conference

Summary:

High-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction level they operate on typically contains no or limited information on low-level circuit details that power consumption depends on. Dataflow circuits have recently been explored in the HLS context; apart from their ability to achieve performance that is superior to standard HLS-generated circuits, their well-defined structure and computational model offer entirely new opportunities for reasoning about power at the HLS level. This paper exploits this insight to present an accurate switching activity estimator for HLS-produced dataflow circuits. Our estimator combines the knowledge about the dataflow circuit structure with software profiling and detailed glitching analysis to estimate the circuit’s switching activity with an average error rate of 1.8% and average speedup of 17.8× compared with a cycle-accurate simulator. Our technology-agnostic solution makes a critical advancement in HLS power estimation and sets the stage for integrating power optimization within the HLS process.

DynaRapid :
Conference ArODES
fast-tracking from C to routed circuits

Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne

Proceedings of the 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), 2-6 September 2024, Torino, Italy

Link to the conference

Summary:

Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation: while software code compilation may take just a few seconds, FPGA compilation times can often span from several minutes to hours due to the complexity of the underlying toolchain and ever-growing device capacities. In this paper, we present DynaRapid, a fast compilation tool that generates—in a matter of seconds—fully legal placed-and-routed designs for commercial FPGAs. Elastic circuits created by the HLS tool Dynamatic are made exclusively of a limited number of reusable components; we exploit this fact to create a library of placed and routed building blocks, and then stitch together instances of them as needed through RapidWright. Our approach accelerates the C-to-FPGA implementation process by a geomean 20× with only 10% of degradation in operating frequency compared to a conventional commercial off-the-shelf implementation flow.

Blending scheduling barriers: :
Conference ArODES
a hybrid approach for FPGA-based post-quantum cryptography

Capucine Mien Verone Beger-Sigrist, Andrea Guerrieri

Proceedings of the 25th International Symposium on Quality Electronic Design (ISQED) 2024, 3-5 April 2024, San Francisco, CA, USA

Link to the conference

Summary:

FPGAs hold great promises for Post-Quantum Cryptography (PQC) hardware through the adoption of electronic design automation tools such as High-Level Synthesis (HLS). Previous works demonstrated how the combination of pragmas and code refactoring techniques significantly enhances the Quality of Results (QoR) [1]. However, manually modifying the original code presents two notable drawbacks: (1) the performance can be suboptimal, and (2) it is highly prone to interpretation that may compromise functionality. In this work, we leverage innovative HLS techniques and tools based on dynamic scheduling, typically not requiring any code alterations to maximize performance to the greatest extent possible. In particular, we highlight the benefits of combining static and dynamic HLS while designing PQC and how it opens up new challenges for further research in this field.

DynaRapid :
Conference ArODES
from C to FPGA in a few seconds

Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne

Proceedings of the FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 3-5 March 2024, Monterey, CA, USA

Link to the conference

Survival of the fastest :
Conference ArODES
enabling more out-of-order execution in dataflow circuits

Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'24), 3-5 March 2024, Monterey, CA, USA

Link to the conference

Summary:

Dynamically scheduled HLS, through dataflow circuit generation, has proven successful at exploiting operation-level parallelism in several important situations where statically scheduled HLS fails. Yet, although existing dataflow circuits support out-of-order execution of different operations, they strictly confine successive instances of the same operation to execute sequentially in program order, which drastically affects the circuit's performance in the presence of a long-latency operation. This is in stark contrast with the reordering freedom customary in superscalar processors that naturally exploit qualitatively more parallelism in a broad class of applications. The goal of this work is to produce dataflow circuits that have reordering capabilities closer to those of out-of-order superscalar processors. This can bring dramatic improvements in some practically important cases, including when outer iterations in nested loops are independent and the inner loop execution has an unavoidable large initiation interval. In various cases, our technique increases throughput by a factor dependent on the initiation interval of the kernel, at a comparatively modest area cost.

2023

H-Saber :
Conference ArODES
an FPGA-optimized version for designing fast and efficient post-quantum cryptography hardware accelerators

Andrea Guerrieri, Gabriel da Silva Marques, Francesco Regazzoni, Andres Upegui

Proceedings of the 2023 24th International Symposium on Quality Electronic Design (ISQED), 5-7 April 2023, San Francisco, CA, USA

Link to the conference

Summary:

With the performance promises of quantum computers, standard encryption algorithms can be defeated. For this reason, a set of new quantum-resistant algorithms have been proposed and submitted for a standardization contest initiated by NIST. While the submission requirement was ANSI C for the reference implementation, NIST encouraged providing software implementations optimized for different target platforms, such as high-performance CPUs, embedded microcontrollers, and FPGAs. Yet, none of the algorithms submitted any FPGA-optimized code, due to the large and expensive development time required for coding at RTL. High-Level synthesis (HLS) covers the gap by creating automatically hardware code for FPGA out of C/C++. However, the quality of results is suboptimal due to the limitation imposed by the inadequacy of source code for HLS. In this paper, we propose a version of Saber’s code optimized for FPGA targets. We show how we detected and improved the performance of the reference code, achieving competitive results compared to the hand-made RTL-based designs.

2022

Optimizing lattice-based post-quantum cryptography codes for high-level synthesis
Conference ArODES

Andrea Guerrieri, Francesco Regazzoni, Andres Upegui

Proceedings of the 2022 25th Euromicro Conference on Digital System Design (DSD), 31 August-2 September 2022, Maspalomas, Spain

Link to the conference

Summary:

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes the QoR (Quality of Results) can be sub-optimal due to the difficulties of HLS in handling general-purpose software code. In this paper, we explore the current difficulties of HLS while synthesizing Lattice-based Post-Quantum Cryptog-raphy (PQC) algorithms. We propose code-level optimizations to overcome the limitations of high-level synthesis increasing the QoR of generated hardware. We analyzed and improved the results for the algorithms competing in the 3rd round of the NIST standardization process. We show how, starting from the original reference code submitted for the competition, original performance and resource utilization can be improved, in some cases with a speedup factor up to 200× or an area reduction of 80%.

FCCM'22
Conference

Guerrieri Andrea

Field Custom Computing Machines (FCCM), 15.05.2022 - 18.05.2022, Cornell Tech, New York City, New York, USA

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