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Berthet Quentin

Professeur-e HES assistant-e (PAPTC)

Main skills

Professeur-e HES assistant-e (PAPTC)

Desktop: I309

Haute école du paysage, d'ingénierie et d'architecture de Genève
Rue de la Prairie 4, 1202 Genève, CH

Faculty
Technique et IT

Main Degree Programme
Informatique et systèmes de communication

Institute
inTECH - Institut d’ingénierie industrielle et informatique

BSC HES-SO en Informatique et systèmes de communication - Haute école du paysage, d'ingénierie et d'architecture de Genève

Systèmes logiques
Électronique
Conception of Hardware Systems
Smart Devices
Computer Architecture

Ongoing

NORA - Noise Radar

Role: Collaborator

Requérant(e)s: Meleder Glenn, Securaxis

Financement: Innosuisse

Description du projet :

Urban environments are exposed to high noise levels that have an impact on human health. Road traffic is a prominent factor of noise pollution. The NORA project aims to address this problem by developing an adaptive cloud-edge platform based on FPGA devices for smart cities by combining IoT, acoustic and AI.

Research team within HES-SO: Upegui Posada Andres , Abdennadher Nabil , Berthet Quentin , Poleggi Marco Emilio

Partenaires académiques: Lissek Hervé, EPFL

Partenaires professionnels: Meleder Glenn, Securaxis

Durée du projet: 01.02.2021 - 31.12.2023

Montant global du projet: 686'605 CHF

Url of the project site: https://lsds.hesge.ch/nora-noise-radar-distributed-acoustic-sensor-network-for-traffic-noise-impact-measurement/

Statut: Ongoing

Completed

Capidel - Capteur tactile capillaire avec IA embarquée pour robotique

Role: Collaborator

Financement: HES-SO

Description du projet :

Capteur tactile avec capillaires et intelligence embarquée pour des manipulations robotiques délicates

Research team within HES-SO: Upegui Posada Andres , Lopez De Meneses Yuri , Llera Miguel , Gantel Laurent , Berthet Quentin

Durée du projet: - 15.11.2023

Montant global du projet: 220'000 CHF

Statut: Completed

SOMA - Self Organising Machine Architecture

Role: Collaborator

Financement: Fonds National Suisse

Description du projet :

SOMA is an adaptive reconfigurable architecture to the extent that it will dynamically re-organize both its computation and its communication by adapting itself to the data to process. SOMA is based on cellular computing since it targets a massively parallel, distributed and decentralized neuromorphic architecture. SOMA is a neuromorphic hardware system since its organization emerges from the interactions between neural maps transposed into hardware from brain observation.

Research team within HES-SO: Upegui Posada Andres , Vannel Fabien , Schmidt Joachim , Berthet Quentin , Barrientos Diego

Partenaires académiques: Benoït Miramond, Université de Nice; Bernard Girau, Université de Lorraine; Nicolas Rougier, INRIA - Bordeaux

Durée du projet: 01.03.2018 - 01.12.2021

Montant global du projet: 461'238 CHF

Url of the project site: https://www.hes-so.ch/fr/self-organizing-machine-architecture-soma-13298.html

Publications liées:

Statut: Completed

DyReCte - Dynamically Reconfigurable Cryptoengine

Role: Collaborator

Financement: Innosuisse

Description du projet :

Ce projet a deux objectifs : 1) Développer un cœur de calcul sur une architecture matérielle pour implémenter des algorithmes de cryptographie post-quantique et 2) Concevoir et implémenter une architecture FPGA dynamiquement reconfigurable pour des nano-satellites. Cette architecture fournira des capacités de tolérance aux pannes et permettra de sécuriser les communications entre le satellite et la terre.

Research team within HES-SO: Upegui Posada Andres , Berthet Quentin , Gantel Laurent , Guerrieri Andrea , Da Silva Marques Gabriel

Partenaires académiques: Duc Alexandre, HEIG-VD

Partenaires professionnels: Felk Yacine, Cysec S.A.

Durée du projet: 17.06.2019 - 17.06.2021

Montant global du projet: 417'770 CHF

Statut: Completed

2022

A unified software/hardware scalable architecture for brain-inspired computing based on self-organizing neural models

Scientific paper ArODES

Artem R. Muliukov, Laurent Rodriguez, Benoit Miramond, Lyes Khacef, Joachim Schmidt, Quentin Berthet, Andres Upegui

Frontiers in Neuroscience, 2022, vol. 16, article no. 825879

Link to the publication

Summary:

The field of artificial intelligence has significantly advanced over the past decades, inspired by discoveries from the fields of biology and neuroscience. The idea of this work is inspired by the process of self-organization of cortical areas in the human brain from both afferent and lateral/internal connections. In this work, we develop a brain-inspired neural model associating Self-Organizing Maps (SOM) and Hebbian learning in the Reentrant SOM (ReSOM) model. The framework is applied to multimodal classification problems. Compared to existing methods based on unsupervised learning with post-labeling, the model enhances the state-of-the-art results. This work also demonstrates the distributed and scalable nature of the model through both simulation results and hardware execution on a dedicated FPGA-based platform named SCALP (Self-configurable 3D Cellular Adaptive Platform). SCALP boards can be interconnected in a modular way to support the structure of the neural model. Such a unified software and hardware approach enables the processing to be scaled and allows information from several modalities to be merged dynamically. The deployment on hardware boards provides performance results of parallel execution on several devices, with the communication between each board through dedicated serial links. The proposed unified architecture, composed of the ReSOM model and the SCALP hardware platform, demonstrates a significant increase in accuracy thanks to multimodal association, and a good trade-off between latency and power consumption compared to a centralized GPU implementation.

Hardware architecture for asynchronous cellular self-organizing maps

Scientific paper ArODES

Quentin Berthet, Joachim Schmidt, Andres Upegui

Electronics, 2022, vol. 11, no. 2, articl no. 215

Link to the publication

Summary:

Nowadays, one of the main challenges in computer architectures is scalability; indeed, novel processor architectures can include thousands of processing elements on a single chip and using them efficiently remains a big issue. An interesting source of inspiration for handling scalability is the mammalian brain and different works on neuromorphic computation have attempted to address this question. The Self-configurable 3D Cellular Adaptive Platform (SCALP) has been designed with the goal of prototyping such types of systems and has led to the proposal of the Cellular Self-Organizing Maps (CSOM) algorithm. In this paper, we present a hardware architecture for CSOM in the form of interconnected neural units with the specific property of supporting an asynchronous deployment on a multi-FPGA 3D array. The Asynchronous CSOM (ACSOM) algorithm exploits the underlying Network-on-Chip structure to be provided by SCALP in order to overcome the multi-path propagation issue presented by a straightforward CSOM implementation. We explore its behaviour under different map topologies and scalar representations. The results suggest that a larger network size with low precision coding obtains an optimal ratio between algorithm accuracy and FPGA resources.

Hardware Architecture for Asynchronous Cellular Self-Organizing Maps

Scientific paper

Berthet Quentin, Schmidt Joachim, Upegui Posada Andres

Electronics (MDPI), 2022

Link to the publication

A unified software/hardware scalable architecture for brain-inspired computing based on self-organizing neural models

Scientific paper

Artem Muliukov, Laurent Rodriguez, Benoit Miramond, Lyes Khacef, Berthet Quentin, Schmidt Joachim, Upegui Posada Andres

Frontiers in Neuroscience, 2022

Link to the publication

Summary:

The field of artificial intelligence has significantly advanced over the past decades, inspired by discoveries from the fields of biology and neuroscience. The idea of this work is inspired by the process of self-organization of cortical areas in the human brain from both afferent and lateral/internal connections. In this work, we develop an original brain-inspired neural model associating Self-Organizing Maps (SOM) and Hebbian learning in the Reentrant SOM (ReSOM) model. The framework is applied to multimodal classification problems. Compared to existing methods based on unsupervised learning with post-labeling, the model enhances the state-of-the-art results. This work also demonstrates the distributed and scalable nature of the model through both simulation results and hardware execution on a dedicated FPGA-based platform named SCALP (Self-configurable 3D Cellular Adaptive Platform). SCALP boards can be interconnected in a modular way to support the structure of the neural model. Such a unified software and hardware approach enables the processing to be scaled and allows information from several modalities to be merged dynamically. The deployment on hardware boards provides performance results of parallel execution on several devices, with the communication between each board through dedicated serial links. The proposed unified architecture, composed of the ReSOM model and the SCALP hardware platform, demonstrates a significant increase in accuracy thanks to multimodal association, and a good trade-off between latency and power consumption compared to a centralized GPU implementation.

2021

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

Scientific paper

Gantel Laurent, Berthet Quentin, Emna Amri, Alexandre Karlov, Upegui Posada Andres

Electronics (MDPI), 2021 , vol. 10, no 17

Link to the publication

Summary:

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

An Area-Efficient SPHINCS+ Post-Quantum Signature Coprocessor

Scientific paper

Berthet Quentin, Upegui Posada Andres, Gantel Laurent, Duc Alexandre, Giulia Traverso

2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2021

Link to the publication

2021

An area-efficient SPHINCS+ post-quantum signature coprocessor

Conference ArODES

Quentin Berthet, Andres Upegui, Laurent Gantel, Alexandre Duc

Proceedings of 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 17-21 June 2021, Portland, OR, USA

Link to the conference

Summary:

The significant advances in the area of quantum computing of the past decade leave no doubt about the fact that quantum computers are an actual threat to cryptography. For this reason, a lot of efforts have been made lately in designing so-called post-quantum cryptographic primitives. The adoption of these schemes depends on the future capability of post-quantum cryptographic schemes to offer performances and functionalities similar to their classical counterparts. In particular, a milestone towards standardization is the implementation on FPGA of cryptographic primitives which leads to an efficient execution. We contribute in this respect by providing an area-efficient FPGA implementation of SPHINCS + , a post-quantum signature scheme which guarantees very high security, allowing its deployment into embedded systems such as hardware security modules, IoT devices or nanosatellites.

Achievements

PEOPLE@HES-SO
Directory and Skills inventory

Berthet Quentin

Professeur-e HES assistant-e (PAPTC)

Main skills

FPGA

Embedded Systems

Microcontrollers

Computer Architecture

Machine Learning

Professeur-e HES assistant-e (PAPTC)

PEOPLE@HES-SO Directory and Skills inventory

Berthet Quentin

Professeur-e HES assistant-e (PAPTC)

Main skills

FPGA

Embedded Systems

Microcontrollers

Computer Architecture

Machine Learning

Professeur-e HES assistant-e (PAPTC)

PEOPLE@HES-SO
Directory and Skills inventory