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PEOPLE@HES-SO – Directory and Skills inventory
PEOPLE@HES-SO – Directory and Skills inventory

PEOPLE@HES-SO
Directory and Skills inventory

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Gantel Laurent

Gantel Laurent

Adjoint-e scientifique ou artistique HES

Main skills

FPGA

Reconfigurable Architectures

Linux embarqué

Signal Processing (Images/Video)

Heterogeneous Computing

  • Contact

  • Teaching

  • Research

  • Publications

  • Conferences

Main contract

Adjoint-e scientifique ou artistique HES

Desktop: I309

Haute école du paysage, d'ingénierie et d'architecture de Genève
Rue de la Prairie 4, 1202 Genève, CH
hepia
Faculty
Technique et IT
Main Degree Programme
Informatique et systèmes de communication
BSc HES-SO en Ingénierie des technologies de l'information - Haute école du paysage, d'ingénierie et d'architecture de Genève
  • Systèmes logiques
  • FPGA - VHDL
  • FPGA-VHDL-Design of Soc on FPGA
  • Programmation des microcontrôleurs
  • Programmation C/C++

Completed

Capidel - Capteur tactile capillaire avec IA embarquée pour robotique

Role: Collaborator

Financement: HES-SO

Description du projet :

Capteur tactile avec capillaires et intelligence embarquée pour des manipulations robotiques délicates

Research team within HES-SO: Upegui Posada Andres , Lopez De Meneses Yuri , Llera Miguel , Gantel Laurent , Berthet Quentin

Durée du projet: - 15.11.2023

Montant global du projet: 220'000 CHF

Statut: Completed

Prime de soutien au montage de projets Innosuisse - Projet "DyReCte"
AGP

Role: Collaborator

Requérant(e)s: hepia inIT, Upegui Posada Andres, hepia inIT

Financement: HES-SO Rectorat

Description du projet : Prime de soutien au montage de projets Innosuisse - Projet "DyReCte"

Research team within HES-SO: Upegui Posada Andres , Gantel Laurent , Barrientos Diego

Partenaires académiques: hepia inIT; Upegui Posada Andres, hepia inIT

Durée du projet: 01.11.2019 - 31.12.2022

Montant global du projet: 15'000 CHF

Statut: Completed

DyReCte - Dynamically Reconfigurable Cryptoengine

Role: Collaborator

Financement: Innosuisse

Description du projet :

Ce projet a deux objectifs : 1) Développer un cœur de calcul sur une architecture matérielle pour implémenter des algorithmes de cryptographie post-quantique et 2) Concevoir et implémenter une architecture FPGA dynamiquement reconfigurable pour des nano-satellites. Cette architecture fournira des capacités de tolérance aux pannes et permettra de sécuriser les communications entre le satellite et la terre.

Research team within HES-SO: Upegui Posada Andres , Berthet Quentin , Gantel Laurent , Guerrieri Andrea , Da Silva Marques Gabriel

Partenaires académiques: Duc Alexandre, HEIG-VD

Partenaires professionnels: Felk Yacine, Cysec S.A.

Durée du projet: 17.06.2019 - 17.06.2021

Montant global du projet: 417'770 CHF

Statut: Completed

Réseau de capteurs sans fils pour le suivi de l'activité physique des personnes handicapées
AGP

Role: Collaborator

Requérant(e)s: IICT, Perez-Uribe Andres, IICT

Financement: HES-SO Rectorat

Description du projet : Physical inactivity has been identified as a major contributor to the exacerbation of physical illnesses. The WHO identified it as the fourth leading risk factor of global mortality after high blood pressure, tobacco use and high blood glucose. Therefore, in recent years, many actions against inactivity have come to the fore. For instance, diverse pedometer devices have been developed to help people reach certain physical activity goals, like walking 30 minutes per day. However, an equivalent recommendation for disabled people using wheelchairs is missing and the few studies that have dealt with this issue concluded that commercial physical activity measurement devices are not appropriate for them. This project has the objective of developing an embedded physical activity measurement system for disabled people using wheelchairs, by exploiting on-body and wheelchair-mounted wireless sensors. This project will gather together data scientists (Pr. Perez-Uribe), embedded systems designers (Pr. Upegui & Pr. Giandomenico), biomechanics experts (Pr. Schmitt) and Human motricity and handicap experts (Pr. Degache). During the first phase of the project, we will use diverse configurations of sensors (motion, ECG, EMG) to assess the physical activity of able-bodied people on a wheelchair. We will first use off-the-shelf sensors to capture data and apply feature-extraction and machine learning techniques to the sensor readings in order to come-up with non-linear models matching the relationship between raw data and energy expenditure, provided by a portable metabolic cart. In parallel, we will develop our own embedded hardware to optimize size, maximize comfort, and minimize costs. Diverse activities like resting, deskwork, and wheelchair propulsion along different surfaces and slopes will be considered. During the second phase, we will evaluate our system with disabled patients suffering from Spinal Cord Injury in collaboration with the Swiss Paraplegic Centre or the SuvaCare (the HESAV team will submit a project proposal in October to fund their contribution during this phase). The result of this project will be an embedded system for home monitoring of the physical activity of disabled people, which can be used to promote ACTIvity as an antiDOTE to illness exacerbation, and for instance, to track the evolution of mobility during rehabilitation. ACTIDOTE aims at closing a gap regarding the availability of self-tracking/motivational devices among disabled people.

Research team within HES-SO: Upegui Posada Andres , Giandomenico Nicola , Satizabal Mejia Hector Fabio , Charrotton Yannick , Grillon Alexandre , Gantel Laurent , Greppin Christophe , Lescourt Adrien , Rastoll Clément , Perez Uribe Andres , Schmitt Carl

Partenaires académiques: IICT; COMATEC; VD-HESAV; hepia inSTI; hepia inIT; Perez-Uribe Andres, IICT

Durée du projet: 01.12.2014 - 30.09.2016

Montant global du projet: 249'990 CHF

Statut: Completed

AcceleRation on heteRogenous cOmputing hardWare
AGP

Role: Collaborator

Financement: HES-SO Rectorat; VS - Institut Systèmes industriels; ReDS; hepia inIT; FR - EIA - Institut IPRINT; Analyse de données; hepia inIT

Description du projet : " The goal of the project is to develop a prototype of an embedded heterogeneous high performance computation platform based on FPGAs, GPUs, and CPUs. Such platform will provide the possibility to execute a given task on the platform offering the better performances according to the tasks nature. We will mainly focus on the technical aspects concerning system setup and efficient data transmission between the different components of the system. At the end of the project we will present with a demonstrator of an embedded heterogenous computing platform running a real-world application. "

Research team within HES-SO: Upegui Posada Andres , Mudry Pierre-André , Gantel Laurent , Bilat Cédric , Bullot Dominique , Vannel Fabien , Rossier Daniel , Pignat Marc

Durée du projet: 01.05.2013 - 31.10.2014

Montant global du projet: 300'000 CHF

Statut: Completed

Design d'une liaison Ethernet sur fibre optique 10Giga
AGP

Role: Collaborator

Requérant(e)s: ReDS

Financement: HES-SO Rectorat; Socle Ra&D; hepia inIT

Description du projet : L'objectif du projet est de fournir un ensemble de méthodologies, de règles et un design pour la mise en 'uvre de liaisons série à haut débit à 10 Gigabits/sec de façon fiable et efficace. Le but est d'investiguer les différentes étapes de mise en 'uvre d'un lien Ethernet 10Giga, soit: - carte électronique (PCB): règles de routage du PCB, maîtrise des impédances, stack-up, simulation. - transceiver des FPGAs: configuration et réglage, mesure qualité signal, outils EDA. - protocole Ethernet: générateur/analyseur, PCS 10Giga, BER, domaine d'horloge, vérification. Les résultats du projet comprendront un design Ethernet pour 2 technologies de FPGA, un ensemble de règles et de méthodologies, des designs de configuration des transceiver et des tutoriaux sur l'utilisation des outils EDA pour la conception, la réalisation et la validation de lien à 10Giga à l'ensemble des membres de la HES-SO et des PMEs. Le projet permettra la mise en 'uvre d'un générateur de trafic Ethernet 10Giga sur 10 liaisons en parallèle pour tester et valider un système de transmission sécurisée à 100Gigabits/sec.

Research team within HES-SO: Coeudevez Pascal , Petraglio Enrico , Messerli Etienne , Gantel Laurent , Donzelot Christophe , Vannel Fabien , Auberson Olivier , Dolivo Yann

Partenaires académiques: ReDS; IICT

Durée du projet: 01.03.2013 - 30.06.2014

Montant global du projet: 164'100 CHF

Statut: Completed

2023

Applications enabled by FPGA-based technology
Book ArODES

Andres Upegui, Andrea Guerrieri, Laurent Gantel

2023,  Basel : MDPI,  196 p.

Link to the publication

Summary:

This book is a reprint of the Special Issue Applications Enabled by FPGA-Based Technology that was published in Electronics.

Applications enabled by FPGA-based technology
Scientific paper ArODES

Andrea Guerrieri, Andres Upegui, Laurent Gantel

Electronics,  12, 15, 3302

Link to the publication

Applications Enabled by FPGA-Based Technology
Book

Upegui Posada Andres, Guerrieri Andrea, Gantel Laurent

2023,  Basel, Switzerland : MDPI,  198  p.

Link to the publication

Applications enabled by FPGA-based technology
Scientific paper

Guerrieri Andrea, Upegui Posada Andres, Gantel Laurent

Electronics,, 2023

Link to the publication

2021

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application
Scientific paper

Gantel Laurent, Berthet Quentin, Emna Amri, Alexandre Karlov, Upegui Posada Andres

Electronics (MDPI), 2021 , vol.  10, no  17

Link to the publication

Summary:

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

An Area-Efficient SPHINCS+ Post-Quantum Signature Coprocessor
Scientific paper

Berthet Quentin, Upegui Posada Andres, Gantel Laurent, Duc Alexandre, Giulia Traverso

2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2021

Link to the publication

2020

A FPGA-Based Post-Processing and Validation Platform for Random Number Generators
Scientific paper

Upegui Posada Andres, Gantel Laurent, Duc Alexandre, Steiner Lucie, Vannel Fabien, Glück Florent

2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020

2016

A wireless sensor-based system for self-tracking activity levels among manual wheelchair users
Book chapter ArODES

Alexandre Grillon, Andres Perez-Uribe, Héctor F. Satizábal, Laurent Gantel, David Da Silva Andrade, Andres Upegui, Francis Degache

eHealth 360° : Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering  (pp. 229-240). 2016,  Cham : Springer

Link to the publication

Summary:

ActiDote —activity as an antidote— is a system for manual wheelchair users that uses wireless sensors to recognize activities of various intensity levels in order to allow self-tracking while providing motivation. In this paper, we describe both the hardware setup and the software pipeline that enable our system to operate. Laboratory tests using multi-modal fusion and machine learning reveal promising results attaining a F1-score classification performance of 0.97 on five different wheelchair-based activities belonging to four intensity levels. Finally, we show that such a low cost system can be used for an easy self-monitoring of physical activity levels among manual wheelchair users.

2021

An area-efficient SPHINCS+ post-quantum signature coprocessor
Conference ArODES

Quentin Berthet, Andres Upegui, Laurent Gantel, Alexandre Duc

Proceedings of 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 17-21 June 2021, Portland, OR, USA

Link to the conference

Summary:

The significant advances in the area of quantum computing of the past decade leave no doubt about the fact that quantum computers are an actual threat to cryptography. For this reason, a lot of efforts have been made lately in designing so-called post-quantum cryptographic primitives. The adoption of these schemes depends on the future capability of post-quantum cryptographic schemes to offer performances and functionalities similar to their classical counterparts. In particular, a milestone towards standardization is the implementation on FPGA of cryptographic primitives which leads to an efficient execution. We contribute in this respect by providing an area-efficient FPGA implementation of SPHINCS + , a post-quantum signature scheme which guarantees very high security, allowing its deployment into embedded systems such as hardware security modules, IoT devices or nanosatellites.

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