A passionated and motivated researcher and lecturer with more than a decade of industrial experience and a proven track of successful research projects and commercial products. PRINCE2® certified in project management, the main field of expertise is on reconfigurable computing for embedded systems based on FPGAs and SoCs. Over the years, I shape my career gaining trust and credibility for the companies by working with passion, integrity and delivering commitments on time.
Recent research projects involve electronic design automation, high-level synthesis, reconfigurable SoC exploiting dynamic partial reconfiguration of FPGAs presented in prestigious international venues and journals.
Senior member of IEEE, author and co-author of multiple technical papers, reviewer for prestigious international conferences and scientific journals, author of the book: “Fundamental of System on Chip Design on Arm Cortex-M Microcontrollers" (https://www.arm.com/resources/education/books/fundamentals-soc)” in collaboration with Arm.
He is also co-author of Dynamatic (http://dynamatic.epfl.ch), the first dynamically scheduled high-level synthesis compiler, and recipient of the Best Paper Award at the International Symposium on Field-Programmable Gate Arrays (FPGA 2020), the premier conference for presentation of advances in FPGA technology, held in Seaside, California (USA).
Main recents projects can be resumed:
Dynamatic : Dynamically-scheduled High-Level Synthesis Compiler (http://dynamatic.epfl.ch)
Dynamatic is an open-source high-level synthesis compiler that produces synchronous dynamically-scheduled circuits from C/C++ code. Dynamatic generates synthesizable RTL which currently targets FPGAs and ASICs and delivers significant performance improvements compared to state-of-the-art commercial HLS tools in applications with irregular memory accesses or control-dominated code. Dynamatic has been presented in multiple conferences and multiple research journals such as IEEE Circuits and System Magazing, and IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. At FPGA’20, Monterey, California has been awarded with Best Paper Award.
Secure and Reliable In-Orbit Reconfiguration (SeRIORe)
SeRIORe takes part of the call “Mesures de Positionnement 2020” from Swiss Space Office and Space Innovation (former Swiss Space Center). The main motivation for the proposed activity is to offer small satellite operators the possibility to perform in-orbit reconfiguration in a secure and reliable way. In this project have been explored, implemented, and tested fault-tolerant mitigation techniques against SEE (Single Level Effects). To list a few, Triple Modular Redundancy (TMR), Lock-step execution, and configuration memory scrubbing combined with the Design Isolation Flow
dynamic-partial reconfiguration for FPGAs. For secure communication, data payload is
encrypted with AES-256 and authenticated using the post-quantum signature scheme
SPHINCS+ [2]. Part of the system developed in this activity has been launched in orbit on
Falcon 9 (B1058.10) from SpaceX, along with 105 microsatellites, CubeSats, PocketQubes, and
orbital transfer vehicles. The rocket liftoff on 13th January 2022 from SLC-40, Cape Canaveral
Space Force Station, Florida.
DyReCte
DyReCte is a collaboration between HEPIA and CYSEC funded by Innosuisse. The project aims
at building a novel solution of Dynamic Partial Reconfiguration of FPGA on post-quantum
cryptography (PQC) for all critical applications requiring high reliability and security. The
finalist algorithms competing in the NIST standardization process such as SPHINCS+, Saber,
Crystals Kyber/Dilithium, and NTRU have been implemented on FPGA. In the frame of the project, advanced and innovative techniques for hardware design such as HLS (High-Level Synthesis) have been adopted, reducing development costs without compromising performance.
Scaling intensity interferometry to higher frequencies
This project is part of an academic cooperation between HEPIA, the Astronomy Department
of the University of Geneva, and EPFL. Since 1957, Hanbury Brown and Twiss proposed a
technique leveraging interferometry, evaluating the correlation of the intensity of the light
signal of two telescopes to infer the size of a star. This technique is still adopted today, but
more powerful computer are needed for big telescopes. The precision of the results depends
strongly on the accuracy of the arrival times of the photons. This project aims to implement
the correlation on a high-performance reconfigurable system on chip (SoC) with an integrated
radio-frequency acquisition front-end, the Zynq UltraScale+ RFSoC. This cutting-edge SoC
technology improves the data transfer between the ADC and the logic, allowing sampling
rates up to 4GS/s.
IGLUNA: a habitat in Space
IGLUNA is a project coordinated by the Swiss Space Center aimed to simulate a habitat on the moon (IGLUNA). In the field of Igluna, the goal of this project is to design the top-level controller of the GrowBot Hub, "An automated and robotized structure with minimal human effort, allowing vegetable production for a space habitat". The system has been implemented on a SoC featuring a CPU and FPGA to meet the real time constraints on top Linux.
A Swiss Technology R&D Initiative Toward the Direct Detection of Nearby Exoplanet
The goal in this project is to develop a custom real-time computer to control the Adaptive optics to compensate the atmosphere effects. This computer acquires images up to 4Kfps, executes the control algorithm and control up to 4K actuators in less than 50us. The control algorithm includes massive floating-point matrix vector multiplications, filtering and arithmetic transformations. The system is based on Intel's Arria10 FPGA. This work has been presented at RTC4AO5 in Paris.joint project with Observatory of Geneva, Hepia and ETH Zurich.
SWIFT: Software Initiated FPGA Threading
This project aims to use the dynamic partial reconfiguration of FPGAs to load and execute different processing modules dynamically on the same FPGA at runtime, providing abstraction mechanisms to create, execute and join FPGA-based concurrent processing functions under software control. The platform has been developed on Xilinx's Zynq COTS SoC. This work has been presented in multiple international locations such as NASA/ESA Conference for Adaptive Hardware and Systems‘18 in Edinburgh and at Space FPGA User Workshop '18 in ESA/ESTEC Noordwijk. - joint project with Syderal SA under SSC(Swiss Space Center) and ESA (European Space Agency) grant.
LEOSoC: An Open-Source Embedded Linux Library to Manage Hardware Accelerator in Heterogeneous SoCs
Modern heterogeneous SoCs (System-on-Chip) contain a set of hard IPs surrounded by an FPGA fabric for hosting custom
hardware accelerators. LEOSoC reduces the development effort required to interface FPGA HAs and making SoCs easy to use for an embedded software developer who is familiar with the semantics of POSIX threads. This work has been presented at FPGA'18 ,Monterey, California.
Designing a RFNoC Block implementing a SISO Processor using High-Level Synthesis
RFNoC is an FPGA open-source processing tool developed by Ettus Research. SISO Processor is one of the basic component used in modern FEC techniques such as Turbo Codes and LDPC. This work shows the RFNoC block development which implement a SISO Processor into FPGA as answer to "The RFNoC & Vivado HLS Challenge" sponsored by Ettus
Research and Xilinx. This work at GRCon'17 , San Diego, California.
Many other projects supervising PhD, Master, or internship students, in example:
DPR for ML: Dynamic Partial Reconfiguration of FPGAs applied to Image Processing for Machine Learning;
Asymmetric Multiprocessing on ARM SoC with dynamic partial reconfiguration support;
SWITCH edu-ID
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