PEOPLE@HES-SO Directory and Skills inventory

Role: Main Applicant

Description du projet : Les objectifs d'identifier une solution de détection d'une personne quittant son lit sans avoir avertit un-e infirmier-ère. Cette solution devra aussi contenir le contrôle de présence de tous les lits, l'activation/déactivation du système dans la chambre et l'alarme nécessaire. Une solution de détection avec un sur-matelas a déjà été testée mais a plusieurs défauts comme des fausses détections, le nettoyage difficile et le prix. Lors d'un PA, nous avons déjà une première version d'un système de détection. Malheureusement, celui-ci n'a pas pu répondre à toutes les difficultés rencontrées. Le but est de pouvoir reprendre et consolider le système pour répondre aux problématiques de détection de jour comme de nuit ainsi que de détecter la personne. La première version est basée sur une Pi4 et une realsense avec du traitement d'images embarqués pour éviter de transmettre les images. Dans ce projet, nous voudrions tester des algorithmes tel que POCO pour détecter la personne et sa position en bord de lit et ne pas la confondre avec la couverture par exemple. Nous aimerions aussi pouvoir finir le système qui peut prévenir le personnel soignant et aller le tester dans les chambres de simulations du CHUV.

Research team within HES-SO: Mosqueron Romuald

Durée du projet: 17.11.2023 - 31.12.2025

Statut: Ongoing

AR-Lounge / ST

Fly-G2: Fast & easy inspection of confined spaces thanks to real-time, edge-cloud based

Role: Main Applicant

Description du projet : L'objectif du PROJET est le « Développement de modules 5G audio-vidéo avec un mécanisme de synchronisation adaptés au fonctionnement sur un réseau privé »

Research team within HES-SO: Miceli Jean-Pierre , Convers Anthony , Péclard Jean-Rémi , Mosqueron Romuald , Da Rocha Carvalho Bruno , Rieder Thomas

Durée du projet: 02.10.2023 - 31.07.2025

Statut: Ongoing

Completed

HELPIE : Système d'extraction de paramètres physiologiques embarqué sur un robot autonome

Role: Main Applicant

Description du projet : This project innovates in the field of drone based photogrammetry, by enabling real-time calculation of scaled 3D models of indoor and close-tostructure environments. This will allow drone operators and industrial experts to view and Online Application Application Number: 59123.1 IP-ICT Application Title: Fly-G2: Fast & easy inspection of confined spaces thanks to real-time, edge-cloud based photogrammetry Main partners and project manager General information 2/41 interact remotely with the 3D models thanks to edge-cloud.

, , , , , , , , , , , , , , , , , , , Research team within HES-SO: Bouteille Cédric Graf Marcel Miceli Jean-Pierre Graf Yoan Convers Anthony Péclard Jean-Rémi Meier Christopher Hänggi Gregory Allemand Adrien Mosqueron Romuald Catel Torres Arzur Gabriel Podolec Peter Da Rocha Carvalho Bruno Rieder Thomas Extrat Bastien Jaccard Anthony Illan Gressin Adrien Cuneo Basile Thullen Basile Gambin Dorian

Durée du projet: 01.02.2022 - 31.07.2024

Statut: Completed

5G Enabled Drone Payload for real-Time Digitalisation of Industrial Assets

Role: Main Applicant

Description du projet : Le but de ce projet est de concevoir un robot capable de mesurer les paramètres physiologiques utiles après la chute d'une personne dite isolée.

Research team within HES-SO: Thoma Yann , Petraglio Enrico , Dassatti Alberto , Miceli Jean-Pierre , Brunner Nicolas , Convers Anthony , Péclard Jean-Rémi , Truan David , Mosqueron Romuald , Auberson Olivier , Podolec Peter , Rodriguez Zaloña Oscar , Extrat Bastien

Partenaires académiques: ReDS

Durée du projet: 01.08.2020 - 31.03.2023

Statut: Completed

4KREPROSYS project designs new components and new integrated systems for the production of 4K TV content covering the needs from indoor studio production up to difficult outdoor large and mobile events such as Olympics or cycling and car races. The innovation is the introduction of HEVC and IP based communications for 4K TV signals carrying both content and service signal for wireless and wired production to achieve high performance and cost effectiveness. The customers are TV production companies and TV broadcasters. The new production systems will achieve new performance (4K) at lower bandwidth and will allow the TV studio infrastructure, traditionally deployed in the field, to become a "virtual" component that can be locally or remotely deployed according to the best logistic solution of the specific TV production.

Role: Main Applicant

Description du projet : 5G Enabled Drone Payload for real-Time Digitalisation of Industrial Assets

Research team within HES-SO: Medwed Gregory , Miceli Jean-Pierre , Convers Anthony , Pignat Eliéva , De Figueiredo Joackim , Mosqueron Romuald , Auberson Olivier , Joly Kevin , Melehi Bilal , Matthey Gaëtan

Durée du projet: 01.11.2019 - 28.02.2021

Statut: Completed

Role: Main Applicant

Description du projet : L'objectif du projet est d'implanter un codec HEVC très basse latence dans un système hardware basé sur FPGA. Ce projet comprend 5 modules (ci-après désignés WP : Work Packages) résumés comme suit : ' WP1 : Spécifications du codec et du système. ' WP2 : Implantation du codec HEVC basse latence. ' WP3 : Implantation de la couche système TS et Ethernet. ' WP4 : Tests et validation. ' WP5 : Rédaction de documents (articles, datasheet). Le tableau présenté au point 8 donne le plan de travail du projet. A vérifer: Typologie - Type de financement - Type de taux

Research team within HES-SO: Miceli Jean-Pierre , Convers Anthony , Mosqueron Romuald , Auberson Olivier , Matthey Gaëtan

Durée du projet: 01.01.2017 - 31.12.2018

Statut: Completed

2024

Mobilité dans les parcs d'affaires intelligents :

Professional paper ArODES

intégration du concept "Transport as a Service"

Roland Scherwey, Romuald Mosqueron, Marc-Antoine Fénart, Gabriel Python

bulletin.ch = Fachzeitschrift und Verbandsinformationen von Electrosuisse und VSE = Bulletin SEV/AES : revue spécialisée et informations des associations Electrosuisse et AES, 2024, 2, 2-6

Summary:

En combinant numérisation, trafic automatisé et mobilité durable, le projet TaaS propose une solution novatrice pour optimiser la mobilité au sein des parcs d’affaires. L’intégration de la modélisation et des simulations dans un jumeau numérique permet l’évolution itérative de ces parcs, tout en offrant des perspectives d’application dans divers autres secteurs.

Mobilité dans les parcs d'affaires intelligents : intégration du concept "Transport as a Service"

Scientific paper

Intégration du concept «Transport as a Service»

Scherwey Roland, Mosqueron Romuald, Fénart Marc-Antoine, Python Gabriel, Massimo Fiorin, Robatel Vincent, Brunet Yorick

Electrosuisse - bulletin.ch, 2024 , vol. 106, no 2, pp. 51-55

Summary:

2022

Video hand gestures recognition using depth camera and lightweight CNN

Scientific paper ArODES

David González León, Jade Gröli, Sreenivasa Reddy Yeduri, Daniel Rossier, Romuald Mosqueron, Om Jee Pandey, Linga Reddy Cenkeramaddi

IEEE Sensors Journal, 2022, vol. 22, no. 14, pp. 14610-14619

Summary:

Hand gestures are a well-known and intuitive method of human-computer interaction. The majority of the research has concentrated on hand gesture recognition from the RGB images, however, little work has been done on recognition from videos. In addition, RGB cameras are not robust in varying lighting conditions. Motivated by this, we present the video based hand gestures recognition using the depth camera and a light weight convolutional neural network (CNN) model. We constructed a dataset and then used a light weight CNN model to detect and classify hand movements efficiently. We also examined the classification accuracy with a limited number of frames in a video gesture. We compare the depth camera’s video gesture recognition performance to that of the RGB camera. We evaluate the proposed model’s performance on edge computing devices and compare to benchmark models in terms of accuracy and inference time. The proposed model results in an accuracy of 99.48% on the RGB version of test dataset and 99.18% on the depth version of test dataset. Finally, we compare the accuracy of the proposed light weight CNN model with the state-of-the hand gesture classification models.

2011

Generation of hardware/software systems based on CAL dataflow description

Book chapter ArODES

Richard Thavot, Romuald Mosqueron, Julien Dubois, Marco Mattavelli

Dans Erdogan, Ahmet, Gogniat, Guy, Milojevic, Dragomir, Morawiec, Adam, Algorithm-architecture matching for signal and image processing (18 p.). 2011, Dodrecht : Springer

Summary:

This chapter presents a new development of rapid prototyping tools for system design based on data-flow specifications. In this context, the efficiency of tools for the automatic translation from the data-flow programs to C and/or HDL are assessed by means of two design cases. The chapter also introduces the new concept of the automatic synthesis of interfaces. Such generic interfaces are implemented by using an embedded microprocessor, which can support a large variety of interfaces already available as native IP libraries in the case of FPGA. The two design cases described here have been developed, tested and validated on different implementation platforms. The results of the assessment show that flexibility, genericity and generality are attractive features of the proposed interface implementation methodology approach.

2008

Smart camera based on embedded HW/SW coprocessor

Scientific paper ArODES

Romuald Mosqueron, Julien Dubois, Marco Mattavelli, David Mauvilet

EURASIP Journal on Embedded Systems, 2008, 1, 597872

Summary:

This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the coprocessor unit is integrated into the image acquisition loop. The acquisition and coprocessing architecture are compatible with the majority of CMOS sensors. It enables the dynamic selection of a wide variety of acquisition modes as well as the reconfiguration and implementation of high-performance image preprocessing algorithms (calibration, filtering, denoising, binarization, pattern recognition). Furthermore, the processing and data transfer, from the CMOS sensor to the processor, can be operated simultaneously to increase achievable performances. The coprocessor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing stages (up to 8 successive predefined preprocessing stages), during the image acquisition process that can be defined by the user according to each specific application requirement. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the achievable performances.

2007

High-speed smart camera with high resolution

Scientific paper ArODES

Romuald Mosqueron, Julien Dubois, Michel Paindavoine

EURASIP Journal on Embedded Systems, 2007, 024163

Summary:

High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded processing. Two types of algorithms have been implemented. A compression algorithm, specific to high-speed imaging constraints, has been implemented. This implementation allows to reduce the large data flow (6.55 Gbps) and to propose a transfer on a serial output link (USB 2.0). The second type of algorithm is dedicated to feature extraction such as edge detection, markers extraction, or image analysis, wavelet analysis, and object tracking. These image processing algorithms have been implemented into an FPGA embedded inside the camera. These implementations are low-cost in terms of hardware resources. This FPGA technology allows us to process in real time 500 images per second with a 1280×1024 resolution. This camera system is a reconfigurable platform, other image processing algorithms can be implemented.

2019

An heterogeneous compiler of dataflow programs for zynq platforms

Conference ArODES

Endri Bezati, Simone Casale-Brunet, Romuald Mosqueron, Marco Mattavelli

Proceedings of ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 12-17 May 2019, Brighton, UK

Summary:

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such platforms require to the designer either to modify the software or hardware based designs to obtain higher performance implementations. Thus, the developer needs to either rewrite functional blocks in HDL or to use high-level synthesis of C-like sequential languages with platform locked extensions. In this paper, a compiler infrastructure that takes as input a single behavioral representation, expressed in high-level dataflow RVC-CAL language, is proposed for programming any of the components of heterogeneous Zynq MPSoCs platforms without the need of modifying any line of code on the design.

New noise reduction method based on FPGA for a stereoscopic video system

Conference ArODES

Romuald Mosqueron, Flavio Capitao, Léandre Bolomey, Ietxu Gomez

Proceedings Volume 11172, Fourteenth International Conference on Quality Control by Artificial Vision, 15-17 May 2019, Mulhouse, France

Summary:

A 3D reality world used for medical therapies needs clear images without defective and noisy pixels. This is essential for portative equipments used by several patients inside the same building. To reduce the resources of the system, a corrective and denoising implementation has been implemented based on FPGA. Two low resources algorithms are proposed for defective pixel correction and noise reduction. The correction algorithms are integrated according to ”Bayer Color Filter Array” for stereoscopic video system respecting real-time constraints. State-of-the-art denoising algorithm shows that implementations use too many resources for the target system, therefore a new low resource denoising algorithm is presented. It is derived from the efficient Non-Local Means (NLM) denoising algorithm which is hardly implementable in a FPGA system. The new denoising method discussed in this paper does not use any multiplier and only consumes 3.8k ALUTs.

2010

Automatic multi-connectivity interface generation for system designs based on a dataflow description

Conference ArODES

Richard Thavot, Ab Al-Hadi Ab Rahman, Romuald Mosqueron, Marco Mattavelli

Proceedings of the 6th Conference on Ph.D. Research in Microelectronics & Electronics, 18-21 July 2010, Berlin Germany

Summary:

This paper presents a contribution to the development of rapid prototyping tools based on dataflow description. In this context, a major key goal is to propose a design flow which includes an automatic synthesis of the hardware interfaces. Therefore, this paper presents a methodology to define and generate automatically a system's interface from a data-flow description. To achieve such an ambitious goal, a generic hardware socket has been defined. This paper presents especially the serialization and de-serialization of different data flows between the hardware design and the physical interface. Different strategies are therefore compared and discussed.

2009

Motion estimation accelerator with user search strategy in an RVC context

Conference ArODES

Julien Dubois, Richard Thavot, Romuald Mosqueron, Johel Miteran, Christophe Lucarz

Proceedings of the 16th IEEE International Conference on Image Processing (ICIP), 7-10 Noember 2009, Cairo, Egpyt

Summary:

Motion estimation represents a key module in video compression. The RVC context requires proposing a flexible solution for motion estimation. According to the nature of the application, a full search is sometimes not suitable, hence, alternative fast/reduced solutions should be considered. This paper proposes a model and implementation of a flexible motion estimation engine, which can be configured to support any user-defined search strategy. Typically, the computational requirements of the search strategy can be traded with the RD-performance of the obtained video encoder. A CAL dataflow description of the accelerator is proposed so that it can be easily handled in the RVC context. An automatic translation of the proposed CAL module to HDL is performed, and a comparison between the generated HDL with handwritten HDL code of the same model is performed. This helps to evaluate the influences of the CAL model refinements.

Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

Conference ArODES

Richard Thavot, Romuald Mosqueron, Julien Dubois, Marco Mattavelli

Proceedngs of the DASIP, 22-24 September 2009, Sophia Antipolis, France

Summary:

This paper presents a contribution to the development of rapid prototyping tools based on dataflow description. In this context, the efficiency of automatic translator tools from the data-flow description to C and/or HDL are presented using two design cases. Moreover, this paper presents the novel concept of the automatic synthesis of interfaces based on dataflow description. Such “generic” interfaces include an embedded microprocessor, which enables using a vide variety of interfaces already available as optimized libraries from the FPGA manufacturers. The different design cases described have been tested and validated on different platforms. The results of the work show the flexibility and generality of the proposed wrapper methodology that is described in the paper.

2008

Dataflow design of a co-processor architecture for image processing

Conference ArODES

Richard Thavot, Romuald Mosqueron, Mohammad Alisafaee, Christophe Lucarz, Marco Mattavelli, Julien Dubois, Vincent Noel

Conference on Design and Architectures for Signal and Image Processing , DASIP 2008, Bruxelles, Belgium, 24-26 November 2008

Summary:

This paper presents the comparison of two design methodologies applied to the design of a co-processor dedicated to image processing. The first methodology is the classical development based on specifying the architecture by directly writing a HDL model using VHDL or Verilog. The second methodology is based on specifying the architecture by using a high level dataflow language followed then by direct synthesis to HDL. The priciple of developing a dataflow description consists on defining a network of autonomous entities called actors, which can communicate only by sending and receiving data tokens. Each entity in the process of consuming and generating data tokens performs completely independent and concurrent processing. A heterogeneous platform composed by a SW processor and the designed HW co-processor is used to compare the results of the designs obtained by the two different methodologies. The comparison of the results shows that the implementations based on the dataflow methodology, not only can be completed with an important reduction of design and development time, but also enable efficient re-design iterations capable of achieving performances, which are comparable in efficiency to design obtained by hand written HDL.

High-speed smart camera with embedded feature extractions and profilometry measurements

Conference ArODES

Julien Dubois, Romuald Mosqueron, Michel Paindavoine, Franck Beguin, Cédric Clerc, Khalil Khattab

Optical and Digital Image Processing

Summary:

Nowadays, high-speed imaging offers high investigation possibilities for a wide variety of applications such as motion study, manufacturing developments. Moreover, due to the electronic progresses, real-time processing can be implemented in the high-speed acquisition systems. Important information can be extracted in real-time from the image and then be used for on-line controls. Therefore we have developed a high-speed smart camera with high-speed CMOS sensor, typically 500 fps with a 1.3 Mega-pixels resolution. Different specific processing have been implemented inside an embedded FPGA according to the high-speed data-flow. The processing are mainly dedicated to feature extraction such as edge detection, or image analysis, and finally markers extraction and profilometry. In any case, the data processing allows to reduce the large data flow (6.55 Gbps) and to propose a transfer on a simple serial output link as USB 2.0. This paper presents the high-speed smart camera and focuses two processing implementations: the marker extraction and the related profilometry measurement. In the marker extraction mode, the center of mass is determined for each marker by a combination of image filtering. Only the position of the center is transferred via the USB 2.0 link. For profilometry measurements, a simplify algorithm has been implemented at low-cost in term of hardware resources. The positions of the markers or the different object's profiles can be determined in real-time at 500 fps with full resolution image. A higher image rate can be reached with a lower resolution (i.e. 500 000 profiles for a single row image).

Smart camera with embedded co-processor :

Conference ArODES

a postal sorting application

Romuald Mosqueron, Julien Dubois, Marco Mattavelli

Optical and Digital Image Processing

Summary:

This work describes an image acquisition and processing system based on a new co-processor architecture designed for CMOS sensor imaging. The platform permits to configure a wide variety of acquisition modes (random region acquisition, variable image size, multi-exposition image) as well as high-performance image pre-processing (filtering, de-noising, binarisation, pattern recognition). Furthermore, the acquisition is driven by an FPGA, as well as a processing stage followed by a Nexperia processor. The data transfer, from the FPGAs board to the Nexperia processor, can be pipelined to the co-processor to increase achievable throughput performances. The co-processor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing (up to 8 successive pre-defined pre-processing), during the image acquisition process that is dynamically defined by the application. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the performances. For instance the reading of bar codes with applications to postal sorting on a PC platform is limited to about 15 images (letters) per second. The new platform beside resulting more compact and easily installable in hostile environments can successfully analyze up to 50 images/s.

2007

A hardware architecture for fast video object recognition using SVM and Zernike moments

Conference ArODES

Cedric Lemaitre, Johel Miteran, Olivier Aubreton, Romuald Mosqueron

Eighth International Conference on Quality Control by Artificial Vision

Summary:

An architecture for fast video object recognition is proposed. This architecture is based on an approximation of featureextraction function: Zernike moments and an approximation of a classification framework: Support Vector Machines (SVM). We review the principles of the moment-based method and the principles of the approximation method: dithering. We evaluate the performances of two moment-based methods: Hu invariants and Zernike moments. We evaluate the implementation cost of the best method. We review the principles of classification method and present the combination algorithm which consists in rejecting ambiguities in the learning set using SVM decision, before using the learning step of the hyperrectangles-based method. We present result obtained on a standard database: COIL-100. The results are evaluated regarding hardware cost as well as classification performances.

2006

Embedded image processing/compression for high-speed CMOS sensor

Conference ArODES

Romuald Mosqueron, Julien Dubois, Michel Paindavoine

Proceedings of the 14th European Signal Processing Conference, 4-8 September 2006, Florence, Italy

Summary:

High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has made possible the development of high-speed video cameras offering digital outputs, readout flexibility and lower manufacturing costs. In this paper, we proposed a high-speed camera based on CMOS sensor with embedded processing. Two types algorithms have been implemented. The compression algorithm represents the first class for our camera and allows to transfer images using serial output link. The second type is dedicated to feature extraction like edge detection, markers extraction, or image analysis, wavelet analysis and object tracking. These image processing algorithms have been implemented into a FPGA embedded inside the camera. This FPGA technology allows us to process in real time 500 images per second with a 1.280H × 1.024V resolution.

2005

Compression embarquée temps réel pour caméras rapides

Conference ArODES

Romuald Mosqueron, Julien Dubois, Michel Paindavoine

Actes de la Conférence MajecSTIC 2005 : Manifestation des Jeunes Chercheurs francophones dans les domaines des STIC, 16-18 Novembre 2005, Rennes, France

Summary:

Les caméras rapides sont de puissants outils pour étudier, par exemple, la dynamique des fluides ou le déplacement des pièces mécaniques lors d'un processus de fabrication. Nous décrivons dans ce papier, un nouveau type de caméra rapide possédant un fonctionnement original. En effet, outre le fait qu'elle utilise comme d'autres caméras, la grande flexibilité des capteurs CMOS en termes d'acquisition (ROI), elle est novatrice au niveau du transfert des données. Celles-ci pouvant être à la fois traitées et/ou compressées en temps réel au sein même de la caméra. Le transfert peut s'effectuer alors à l'aide d'une simple connection série de type USB 2.0. On réalise ainsi l'économie d'une mémoire embarquée, les données étant directement stockées sur la mémoire d'un PC standard, ce qui permet d'utiliser l'intégralité de ses capacités (grande taille mémoire, évolution constante). En parallèle au développement matérielle de la caméra, nous présenterons les algorithmes de compression intégrés au sein de la caméra, notamment un algorithme nous permettant d'utiliser la caméra à sa plus grande résolution (1280 x 1024 pixels) et avec une fréquence image de 500 par seconde. Son taux de compression est de 20, avec un PSNR supérieur à 30.

High-speed camera with internal real-time image processing

Conference ArODES

Michel Paindavoine, Romuald Mosqueron, Julien Dubois, Cedric Clerc, Jean-Claude Grapin, François Tomasini

Ultrafast X-Ray Detectors, High-Speed Imaging, and Applications

Summary:

High-speed video cameras are powerful tools for investigating for instance the dynamics of fluids or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs have made possible the development of high-speed video cameras offering digital outputs, readout flexibility and lower manufacturing costs. In this field, we designed a new fast CMOS camera with a 1280×1024 pixels resolution at 500 fps. In order to transmit from the camera only useful information from the fast images, we studied some specific algorithms like edge detection, wavelet analysis, image compression and object tracking. These image processing algorithms have been implemented into a FPGA embedded inside the camera. This FPGA technology allows us to process fast images in real time.

High-speed camera with internal real-time image compression

Conference ArODES

Michel Paindavoine, Romuald Mosqueron, Julien Dubois, Cedric Clerc, Jean-Claude Grapin, Lionel Pierrefeu, François Tomasini

26th International Congress on High-Speed Photography and Photonics